1. Field of Technology
The present invention relates to a multiprocessor computer system having a plurality of CPUs (Central Processing Units) which execute respective programs stored in a single memory.
2. Description of Prior Art
Computer systems are well known which are of multiprocessor configuration, having a plurality of CPUs to handle processing for various peripheral circuits and devices, to thereby achieve increased performance. With such a multiprocessor system however, it has been generally necessary in the prior art that respective control programs which are executed by the CPUs are stored in respectively different memories, each connected to a dedicated set of buses, i.e., with each memory only being accessible by a corresponding one of the CPUs.
However the size of a control program which is to be executed by a CPU of a computer system cannot be definitely known until development of the system has been completed. Hence, since the memory size (i.e., amount of memory capacity) that will be required for the control program is not accurately known during development, it is necessary to provide an excess amount of memory capacity. Thus in the case of a multiprocessor system, in which the various CPUs execute respectively different control programs which are stored in respective memories, the overall amount of excess memory capacity will become large.
To overcome this problem, it has been proposed in the prior art that all of the control programs of a multiprocessor system be stored in a single program memory. Such a system is disclosed for example in Japanese Patent Hei 5-289987. With that invention, the respective program memory for two CPUs is connected to respective local buses of the two CPUs. A bus access arbitration circuit performs control of data memory such as to enable access by both of the CPUs.
However since the CPUs execute respectively different processing, they must access respectively different memory areas containing the programs which they execute. The above prior art method of enabling access to data memory does not enable accessing of program memory, stored in a single memory unit (i.e., having only one set of memory addresses) by a plurality of CPUs. Thus, that prior art method cannot be directly applied to the problem of a multi-CPU system in which each of respective control programs which are executed by the various CPUs are stored together in a single memory..
Furthermore if each of the CPUs in such a multiprocessor system are identical devices (i.e., the same model of processor, produced by the same manufacturer) then it can be expected that the respective interrupt vectors that are assigned to various interrupt signals will be identical for each of the CPUs. Hence in the prior art, if all of the programs and routines which are executed by the various CPUs were to be stored in a single memory, it would be impossible for the plurality of CPUs to execute respectively different forms of interrupt handler processing in response to the any specific interrupt signal.
This can be understood by considering for example a very simple case in which each CPU automatically specifies the same interrupt vector in response to an interrupt signal which has been assigned the level 1 (execution priority) status. In that case, if a plurality of various types of interrupt might be assigned the level 1 status, then even if the corresponding interrupt signals were to be supplied to respectively different ones of the plurality of CPUs, all of the level 1 interrupts would have to be processed by the same interrupt handler routine. This is a serious disadvantage.
The term “interrupt vector” is used herein with the general significance of information which is generated in some manner when an interrupt signal is supplied to a CPU, which directs the CPU operation to branch to the starting address of a specific interrupt handler program. The term “bus” as used herein within the terms “local bus” and “common bus” is to be understood as signifying a set of buses which includes at least an address bus and data bus.